⎯
79
⎯
6 F 2 S 0 8 4 6
definite time characteristic. The UV
∗
2 gives the PLC signal UV
∗
2_ALARM through delayed
pick-up timer TU
∗
2.
The UV
∗
2_ALARM can be blocked by incorporated scheme switch [UV
∗
2EN] and the PLC
signal UV
∗
2_BLOCK.
These protections are also available to alarm instantaneously by the PLC signal UV
∗
2_INST_TP.
In addition, there is user programmable voltage threshold UVSBLK and UVGBLK. If all three
phase voltages drop below this setting, then both UV
∗
1 and UV
∗
2 are prevented from operating.
This function can be blocked by the scheme switch [VBLKEN]. The [VBLKEN] should be set to
“OFF” (not used) when the UV elements are used as fault detectors, and set to “ON” (used) when
used for load shedding.
Note: The UVSBLK and UVGBLK must be set lower than any other UV setting values.
Figure 2.4.9.7 UVS1 Undervoltage Protection
+
"ON"
[UVS2EN]
0.00 - 300.00s
&
&
&
TUS2
t
0
t
0
t
0
AB
UVS2 BC
CA
UVS2_ALARM
≥
1
UVS2-CA_ALM
UVS2-AB_ALM
UVS2-BC_ALM
&
&
&
NON UVSBLK
≥
1
≥
1
≥
1
&
&
&
1
UVS2_BLOCK
1865
UVS2_INST_TP
1817
969
970
971
972
457
458
459
Figure 2.4.9.8 UVS2 Undervoltage Protection
Figure 2.4.9.9 UVG1 Undervoltage Protection
≥
1
≥
1
≥
1
UVG1 TRI
≥
1
1
0.00 - 300.00s
TUG1
t
0
t
0
t
0
&
&
&
&
&
&
&
&
&
NON
U GBL
&
"ON"
[VBLKEN]
+
"OFF"
[UVTST]
+
UVGBLK
1
UVG -CA TRI
UVG -BC TRI
UVG -AB TRI
A
UVG1
B
C
UVG1
_
BLOC
K
1868
UVG1_INST_TP
1820
460
461
462
973
974
975
976
"DT"
[IDMT]
[UVG1EN]
+
≥
1
≥
1
≥
1
≥
1
≥
1
UVS1_TRIP
≥
1
1
0.00 - 300.00s
TUS1
t
0
t
0
t
0
&
&
&
&
&
&
&
&
&
NON
U SBL
&
"ON"
[VBLKEN]
+
"OFF"
[UVTST]
+
UVSBLK
1
UVS1-CA_TRIP
UVS -BC TRI
UVS -AB TRI
AB
UVS1
BC
CA
UVS1 BLOC
1864
UVS1_INST_TP
1816
454
455
456
965
966
967
968
"DT"
[IDMT]
[UVS1EN]
+
≥
1
≥
1
Содержание GRZ100 B Series
Страница 264: ... 263 6 F 2 S 0 8 4 6 Appendix A Block Diagram ...
Страница 271: ... 270 6 F 2 S 0 8 4 6 ...
Страница 272: ... 271 6 F 2 S 0 8 4 6 Appendix B Signal List ...
Страница 307: ... 306 6 F 2 S 0 8 4 6 ...
Страница 308: ... 307 6 F 2 S 0 8 4 6 Appendix C Variable Timer List ...
Страница 310: ... 309 6 F 2 S 0 8 4 6 Appendix D Binary Input Output Default Setting List ...
Страница 321: ... 320 6 F 2 S 0 8 4 6 ...
Страница 322: ... 321 6 F 2 S 0 8 4 6 Appendix E Details of Relay Menu and LCD Button Operation ...
Страница 331: ... 330 6 F 2 S 0 8 4 6 ...
Страница 340: ... 339 6 F 2 S 0 8 4 6 Appendix G Typical External Connections ...
Страница 377: ... 376 6 F 2 S 0 8 4 6 ...
Страница 384: ... 383 6 F 2 S 0 8 4 6 Appendix J Return Repair Form ...
Страница 388: ... 387 6 F 2 S 0 8 4 6 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Страница 389: ... 388 6 F 2 S 0 8 4 6 ...
Страница 390: ... 389 6 F 2 S 0 8 4 6 Appendix K Technical Data ...
Страница 401: ... 400 6 F 2 S 0 8 4 6 ...
Страница 402: ... 401 6 F 2 S 0 8 4 6 Appendix L Symbols Used in Scheme Logic ...
Страница 405: ... 404 6 F 2 S 0 8 4 6 ...
Страница 406: ... 405 6 F 2 S 0 8 4 6 Appendix M Example of Setting Calculation ...
Страница 417: ... 416 6 F 2 S 0 8 4 6 ...
Страница 418: ... 417 6 F 2 S 0 8 4 6 Appendix N IEC60870 5 103 Interoperability and Troubleshooting ...
Страница 430: ... 429 6 F 2 S 0 8 4 6 Appendix O Programmable Reset Characteristics and Implementation of Thermal Model to IEC60255 8 ...
Страница 434: ... 433 6 F 2 S 0 8 4 6 Appendix P Inverse Time Characteristics ...
Страница 437: ... 436 6 F 2 S 0 8 4 6 ...
Страница 438: ... 437 6 F 2 S 0 8 4 6 Appendix Q Failed Module Tracing and Replacement ...
Страница 444: ... 443 6 F 2 S 0 8 4 6 Appendix R Ordering ...
Страница 447: ......