ADC JESD Register Map
387
SBAU337 – May 2020
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
Table 2-517. Register 35 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
MODE_2S_141620_IQ = 39
MODE_2S_141220_IQ = 40
MODE_2S_24310_IQ = 41
MODE_2S_24610_IQ = 42
MODE_2S_14610_IQ = 43
MODE_2S_141210_IQ = 44
MODE_2S_42111_IQ = 45
MODE_2S_44840_IQ = 46
MODE_2S_VSWR_24410 = 50
2.5.17 Register 36h (offset = 36h) [reset = 1Eh]
Figure 2-513. Register 36h
7
6
5
4
3
2
1
0
0
0
FB_JESD_MODE
R/W-0h
R/W-0h
R/W-1Eh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset