JESD_SUBCHIP Register Map
185
SBAU337 – May 2020
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
Table 2-85. Register 4F Field Descriptions
Bit
Field
Type
Reset
Description
6-4
TXOCTETPATH7_
CLK_SEL
R/W
7h
Selects the input SERDES-Tx lane clk for data that is normally
supposed to be on STX8.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2-0
TXOCTETPATH6_
CLK_SEL
R/W
6h
Selects the input SERDES-Tx lane clk for data that is normally
supposed to be on STX7.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2.3.42 Register 50h (offset = 50h) [reset = 20h]
Figure 2-83. Register 50h
7
6
5
4
3
2
1
0
RX_TX_LOOP
BACK_FIFO_IN
IT_STATE
RX_TX_LOOPBACK_FIFO_OFFSET
RX_TX_LOOP
BACK_MODE_
TX1
RX_TX_LOOP
BACK_MODE_
TX0
R/W-1h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-86. Register 50 Field Descriptions
Bit
Field
Type
Reset
Description
5-5
RX_TX_LOOPBAC
K_FIFO_INIT_STA
TE
R/W
1h
Init state to release Async-FIFO between ADC_JESD and
DAC_JESD out of reset
0 : Reset State
1 : Func State
4-2
RX_TX_LOOPBAC
K_FIFO_OFFSET
R/W
0h
serdes loopback FIFO read delay i.e. FIFO offset
1-1
RX_TX_LOOPBAC
K_MODE_TX1
R/W
0h
Enables loopback to between ADC_JESD and DAC_JESD for
lanes[5:8]
0 : No loopback
1 : Enable ADC_JESD lanes[5:8]
0-0
RX_TX_LOOPBAC
K_MODE_TX0
R/W
0h
Enables loopback to between ADC_JESD and DAC_JESD for
lanes[1:4]
0 : No loopback
1 : Enable ADC_JESD lanes[1:4]
2.3.43 Register 52h (offset = 52h) [reset = 0h]
Figure 2-84. Register 52h
7
6
5
4
3
2
1
0
TXB_B1_Q_DA
TA_NEGATION
TXB_B1_I_DAT
A_NEGATION
TXB_B0_Q_DA
TA_NEGATION
TXB_B0_I_DAT
A_NEGATION
TXA_B1_Q_DA
TA_NEGATION
TXA_B1_I_DAT
A_NEGATION
TXA_B0_Q_DA
TA_NEGATION
TXA_B0_I_DAT
A_NEGATION
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset