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A. Configuration Options
8799-A2-GB20-10 April 2003
A-19
Table A-7. System Clock Options
System Primary Clock Reference
Possible Settings (STU-C): G.703 Port 1–8, Internal
Default Setting: Internal
Possible Settings (STU-R): DSL Port 1–8, Internal
Default Setting: DSL Port 1
Determines the source of system timing. Failure of the clock specified by this
configuration option will result in automatic fallback to the secondary clock source.
G.703 Port n – Timing is derived from the specified port. To be a valid clock source, the
port must be enabled and must derive its timing from the G.703 port. If the G.703 port is
configured for Bypass mode, then its primary clock source must be configured for G.703.
DSL Port n – Timing is derived from the specified port. To be a valid clock source, the port
must be enabled.
Internal – Timing is derived from the internal oscillator, which provides a Stratum 4
reference.
System Secondary Clock Reference
Possible Settings (STU-C): G.703 Port 1–8, Internal
Default Setting: Internal
Possible Settings (STU-R): DSL Port 1–8, Internal
Default Setting: DSL Port 2
Determines the source of system timing if the primary system clock source fails. If the
secondary clock source fails, the card switches to the internal clock.
G.703 Port
n
– Timing is derived from the specified port. To be a valid clock source, the
port must be enabled and must derive its timing from the G.703 port. To be a valid clock
source, the G.703 port must be enabled and configured for Bypass mode, and Primary
Clock Source must be set to G.703 (see
Table A-4, G.703 Interface Options ).
DSL Port
n
– Timing is derived from the specified port. To be a valid clock source, the port
must be enabled.
Internal – Timing is derived from the internal oscillator, which provides a Stratum 4
reference.