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APPENDIX D REVISION HISTORY
Preliminary User’s Manual U17260EJ3V1UD
643
D.2 Revision History up to Previous Edition
Revisions up to the previous edition are shown below. The “Applied to:” column indicates the chapter in each
edition to which the revision was applied.
(1/2)
Edition Description
Applied
to
Addition of only
µ
PD78F0537D as on-chip debug function model
Throughout
Addition of
Caution 3
to
1.4 Pin Configuration (Top View)
CHAPTER 1 OUTLINE
Addition of description of EXSCL0 to
(2) Non-port pins
in
2.1 Pin Function List
Addition of
Caution
to
(2) Control mode
in
2.2.3 P20 to P27 (port 2)
Addition of description to
(c) EXSCL0
of
(2) Control mode
in
2.2.7 P60 to P63
(port 6)
Addition of
Note 2
to
Table 2-2 Pin I/O Circuit Types
CHAPTER 2 PIN
FUNCTIONS
Addition of
Cautions 1
,
2
, and
3
to
3.1.2 Bank area (
µ
PD78F0536, 78F0537, and
78F0537D only)
Deletion of descriptions of the FLPMC, PFCMD, and PFS registers
CHAPTER 3 CPU
ARCHITECTURE
Addition of
Remark
to
4.2.7 Port 6
Modification of output latch setting of P60 and P61 in
Table 4-4 Settings of Port
Mode Register and Output Latch When Using Alternate Function
CHAPTER 4 PORT
FUNCTIONS
Addition of
Cautions 2
and
3
to
Figure 5-6 Format of Clock Operation Mode
Select Register (OSCCTL)
CHAPTER 5 CLOCK
GENERATOR
6.4.6 One-shot pulse output operation
•
Modification of
Caution 1
in
(1) One-shot pulse output with software trigger
•
Modification of
Caution
in
(2) One-shot pulse output with external trigger
Modification of
(a) One-shot pulse output by software
and
(b) One-shot pulse
output with external trigger
of
(5) Re-triggering one-shot pulse
in
6.5 Cautions
for 16-Bit Timer/Event Counters 00 and 01
CHAPTER 6 16-BIT
TIMER/EVENT
COUNTERS 00 AND 01
Modification of
Caution
in
(6) Asynchronous serial interface control register 6
(ASICL6)
of
14.3 Registers Controlling Serial Interface UART6
Modification of
Cautions 1
,
2
, and
4
in
Figure 14-10 Format of Asynchronous
Serial Interface Control Register 6 (ASICL6)
CHAPTER 14 SERIAL
INTERFACE UART6
Modification of description in
(7) Port mode register 6 (PM6)
of
16.3 Registers to
Control Serial Interface IIC0
Addition of “WREL0 = WTIM0 = 1” to “ACKE0 = 0” in
Figure 16-23 Master
Operation Flowchart (1)
and
Figure 16-24 Master Operation Flowchart (2)
CHAPTER 16 SERIAL
INTERFACE IIC0
Modification of
20.2.1 HALT mode
Addition of
Caution 4
to
Table 20-3 Operating Statuses in STOP Mode
CHAPTER 20 STANDBY
FUNCTION
Addition of
Note
to
Figure 22-2 Timing of Internal Reset Signal Generation in
Power-on-Clear Circuit
CHAPTER 22 POWER-
ON-CLEAR CIRCUIT
Change of value of operation stabilization time in
CHAPTER 23 LOW-VOLTAGE
DETECTOR
to 10
µ
s (TYP.) and addition of
Note
“This value may change after
evaluation.”
CHAPTER 23 LOW-
VOLTAGE DETECTOR
Modification of transfer rate
in
25.6 (2) UART6
Modification of transfer rate and deletion of
Notes 2
in Speed column of UART in
Table 25-7. Communication Modes
2nd
edition
Modification of description in
25.9 Flash Memory Programming by Self-Writing
CHAPTER 25 FLASH
MEMORY
Содержание 78K/0 Series
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