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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Preliminary User’s Manual U17260EJ3V1UD
213
7.4.5 Free-running timer operation
When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 01 (free-
running timer mode), 16-bit timer/event counter 0n continues counting up in synchronization with the count clock.
When it has counted up to FFFFH, the overflow flag (OVF0n) is set to 1 at the next clock, and TM0n is cleared (to
0000H) and continues counting. Clear OVF0n to 0 by executing the CLR instruction via software.
The following three types of free-running timer operations are available.
•
Both CR00n and CR01n are used as compare registers.
•
One of CR00n or CR01n is used as a compare register and the other is used as a capture register.
•
Both CR00n and CR01n are used as capture registers.
Remarks 1.
For the setting of the I/O pins, see
7.3 (5) Port mode register 0 (PM0)
.
2.
For how to enable the INTTM00n signal interrupt, see
CHAPTER 19 INTERRUPT FUNCTIONS
.
(1) Free-running timer mode operation
(CR00n: compare register, CR01n: compare register)
Figure 7-37. Block Diagram of Free-Running Timer Mode
(CR00n: Compare Register, CR01n: Compare Register)
Timer counter
(TM0n)
Output
controller
Compare register
(CR01n)
Match signal
TO0n pin
Match signal
Interrupt signal
(INTTM00n)
Interrupt signal
(INTTM01n)
Compare register
(CR00n)
Operable bits
TMC0n3, TMC0n2
Count clock
Remark
n = 0:
µ
PD78F0531, 78F0532, 78F0533
n = 0, 1:
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
Содержание 78K/0 Series
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