APPENDIX D REVISION HISTORY
Preliminary User’s Manual U17260EJ3V1UD
638
(3/7)
Page Description
p. 161
Addition of
Remark
to
Figure 6-14 CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is
Set (Option Byte: POCMODE = 0))
pp. 162 to 165
Modification of the following items in
Table 6-5 CPU Clock Transition and SFR Register Setting
Examples
(3) CPU operating with subsystem clock (D) after reset release (A)
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
p. 166
Modification of
Table 6-6 Changing CPU Clock
p. 167
Addition of
6.6.8 Time required for switchover of CPU clock and main system clock
p. 168
Addition of
6.6.9 Conditions before clock oscillation is stopped
p. 169
Addition of
6.6.10 Peripheral Hardware and Source Clocks
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
p. 170
Revision of chapter
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
p. 247
Modification of description in
8.2 (2) 8-bit timer compare register 5n (CR5n)
CHAPTER 9 8-BIT TIMERS H0 AND H1
p. 264
Modification of
Figure 9-2 Block Diagram of 8-Bit Timer H1
p. 265
Modification of description in
(1) 8-bit timer H compare register 0n (CMP0n)
and
(2) 8-bit time r H
compare register 1n (CMP1n)
in
9.2
p. 269
Modification of
Figure 9-6 Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
p. 279
Modification of
Figure 9-12 (e) Operation by changing CMP1n (CMP1n = 02H
→
03H, CMP0n = A5H)
p. 280
Modification of description in
9.4.3 Carrier generator operation (8-bit timer H1 only)
p. 281
Addition of <3> to
Figure 9-13 Transfer Timing
p. 282
Addition of <8> to Setting in
9.4.3
pp. 284, 285
Modification of
(a) Operation when CMP01 = N, CMP11 = N
and
(b) Operation when CMP01 = N, CMP11 =
M
in
Figure 9-15
p. 286
Modification of description in
Figure 9-15 (c) Operation when CMP11 is changed
CHAPTER 11 WATCHDOG TIMER
p. 293
Modification of description in
11.1 Functions of Watchdog Timer
pp. 296, 297
Addition to description in and addition of
Caution 4
to
11.4.1 Controlling operation of watchdog timer
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
p. 302
Addition of
Note 1
and
Cautions 1
and
2
to
Figure 12-2 Format of Clock Output Selection Register
(CKS)
CHAPTER 13 A/D CONVERTER
pp. 305, 306
Modification of the following items in
13.2 Configuration of A/D Converter
(2) Sample & hold circuit
(3) Series resistor string
(5) Successive approximation register (SAR)
(9) AV
REF
pin
p. 309
Addition to
Caution 1
in and addition of
Caution 4
to
Table 13-2 A/D Conversion Time Selection
p. 312
Modification of
Cautions 2
and
3
in
Figure 13-8 Format of Analog Input Channel Specification Register
(ADS)
p. 313
Modification of description in
13.3 (5) A/D port configuration register (ADPC)
p. 313
Modification of
Cautions 1
and
2
in
Figure 13-9 Format of A/D Port Configuration Register (ADPC)
Содержание 78K/0 Series
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