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CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U17260EJ3V1UD
63
Figure 3-12. Correspondence Between Data Memory and Addressing (
µ
PD78F0534)
SFR addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
49152 x 8 bits
F F F F H
F F 0 0 H
F E F F H
F E E 0 H
F E D F H
F B 0 0 H
F A F F H
C 0 0 0 H
B F F F H
0 0 0 0 H
F F 2 0 H
F F 1 F H
F E 2 0 H
F E 1 F H
Register addressing
Short direct
addressing
Reserved
F 8 0 0 H
F 7 F F H
F 4 0 0 H
F 3 F F H
Internal expansion RAM
1024 x 8 bits
Содержание 78K/0 Series
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