NEC 78K/0 Series, Руководство пользователя

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CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U17260EJ3V1UD
55
Figure 3-8. Memory Map (
µ
PD78F0537D)
Internal expansion RAM
6144 x 8 bits
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
32768 x 8 bits
Vector table area
64 x 8 bits
CALLT table area
64 x 8 bits
Program area
1905 x 8 bits
Option byte area
Note1
5 x 8 bits
CALLF entry area
2048 x 8 bits
Program area
Program area
Option byte area
Note1
5 x 8 bits
Boot cluster 0
Note2
Boot cluster 1
Reserved
F F F F H
F F 0 0 H
F E F F H
F E E 0 H
F E D F H
F B 0 0 H
F A F F H
C 0 0 0 H
B F F F H
0 0 4 0 H
0 0 3 F H
0 0 0 0 H
0 0 8 0 H
0 0 7 F H
0 8 0 0 H
0 7 F F H
1 0 0 0 H
0 F F F H
1 0 8 5 H
1 0 8 4 H
1 0 8 0 H
1 0 7 F H
0 0 8 5 H
0 0 8 4 H
7 F F F H
1 F F F H
F 8 0 0 H
F 7 F F H
E 0 0 0 H
D F F F H
8 0 0 0 H
7 F F F H
Flash memory
16384 x 8 bits
(memory bank 0)
(Memory bank 1)
(Memory bank 2)
(Memory bank 3)
0 0 0 0 H
(Memory bank 5)
(Memory bank 4)
Data memory
space
RAM spcae in
which instruction
can be fetched
Program RAM area
Program
memory
space
Bank
area
Common
area
1 0 8 F H
1 0 8 E H
0 0 8 F H
0 0 8 E H
On-chip debug security
ID setting area
Note1
10 x 8 bits
On-chip debug security
ID setting area
Note1
10 x 8 bits
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
IDs to 0085H to 008EH.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 Security
Setting ).