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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Preliminary User’s Manual U17260EJ3V1UD
216
(3) Free-running timer mode operation
(CR00n: capture register, CR01n: capture register)
Figure 7-41. Block Diagram of Free-Running Timer Mode
(CR00n: Capture Register, CR01n: Capture Register)
Timer counter
(TM0n)
Capture register
(CR00n)
Capture
signal
Capture signal
Interrupt signal
(INTTM01n)
Interrupt signal
(INTTM00n)
Capture register
(CR01n)
Operable bits
TMC0n3, TMC0n2
Count clock
Edge
detection
TI00n pin
Edge
detection
TI01n pin
Selector
Remarks 1.
If both CR00n and CR01n are used as capture registers in the free-running timer mode, the output
level of the TO0n pin is not inverted.
However, it can be inverted each time the valid edge of the TI00n pin is detected if bit 1 (TMC0n1)
of 16-bit timer mode control register 0n (TMC0n) is set to 1.
2.
n = 0:
µ
PD78F0531, 78F0532, 78F0533
n = 0, 1:
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
Содержание 78K/0 Series
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