LAPIS Semiconductor ML610421, Руководство пользователя, Страница: 81 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 5 Interrupts (INTs)
5 – 12
5.2.11 Interrupt Request Register 2 (IRQ2)
Address: 0F01AH
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
IRQ2 QI2C0
   
QSAD

QSIO0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
IRQ2 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ2 request flag is set to “1” regardless of the IE2 and MIE values when an interrupt is generated. In this case,
an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE2) is set to “1” and the
master interrupt enable flag (MIE) is set to “1”.
By setting the IRQ2 request flag to “1” by software, an interrupt can be generated.
The corresponding flag of IRQ2 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
•
QSIO0 (bit 0)
QSIO0 is the request flag for the synchronous serial port 0 interrupt (SIO0INT).
QSIO0 Description
0 No request (initial value)
1 Request
•
QSAD (bit 2)
QSAD is the request flag for the successive approximation type A/D converter interrupt (SADINT)
QSAD Description
0 No request (initial value)
1 Request
•
QI2C0 (bit 7)
QI2C0 is the request flag for the I2C bus 0 interrupt (I2C0INT).
QI2C0 Description
0 No request (initial value)
1 Request
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ2) or to the interrupt enable
register (IE2), the interrupt shift cycle starts after the next 1 instruction is executed.