LAPIS Semiconductor ML610421, Руководство пользователя, Страница: 136 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 10 Timers
10 – 1
10. Timers
10.1 Overview
This LSI includes 4 channels of 8-bit timers.
For the input clock, see Chapter 6, “Clock Generation Circuit”.
10.1.1 Features
•
The timer interrupt (TMnINT) is generated when the values of timer counter register (TMnC, n=0 to 3) and timer data
register (TMnD) coincide.
•
A timer configured by combining timer 0 and timer 1 or timer 2 and timer 3 can be used as a 16-bit timer.
•
For the timer clock, the low-speed clock (LSCLK), high-speed time base clock (HTBCLK), or external clock can be
selected.
•
A 16bit-timer 2 & 3 has clock frequency measurement mode, which can count HTBCLK and generates the timer
interrupt (TM3INT) when the count ends. Using the count data to know the frequency by software can determine
more accurate baud-rate.
10.1.2 Configuration
Figure 10-1 shows the configuration of the timers.
TMnCON0: Timer control register 0 TMnCON1: Timer control register 1
TMmD, TMnD: Timer data registers TMmC, TMnC: Timer counter registers
(a) In 8-bit Timer Mode (Timers 0 to 3)
(b) 16-bit Timer Mode (Timers 0 to 3)
TMnC
8
Data bus
TMnINT
LSCLK
TMnCON0
TMnCON1
R
Match
TMnD
Comparator
8
HTBCLK
8
n = 0 to 3
Write TMnC
TnCK
8
External clock
P44/T02P0CK
P45/T13P1CK
TMnC
TMmINT
LSCLK
TMnCON0
TMnCON1
R
Match
Comparator
HTBCLK
n = 0, 2 m = 1, 3
Write TMmC
TnCK
Write TMnC
TMnD TMmD TMmC
R
8
8
16
8 8
16
External clock
P44/T02P0CK
P45/T13P1CK
Data bus
8
8
8 8
TMmC latch
Read TMnC