LAPIS Semiconductor ML610421, Руководство пользователя, Страница: 173 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 13 Watchdog Timer
12 – 1
12. Watchdog Timer
12.1 Overview
This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in
order to detect an undefined state of the MCU and return from that state.
If the WDT counter overflows due to the failure of clearing of the WDT counter within the WDT overflow period, the
watchdog timer requests a WDT interrupt (non-maskable interrupt). When the second overflow occurs, the watchdog
timer generates a WDT reset signal and shifts the mode to a system reset mode.
For interrupts see Chapter 5, “Interrupts,” and for WDT interrupt see Chapter 3, “Reset Function”.
12.1.1 Features
•
Free running (cannot be stopped)
•
One of four types of overflow periods (125ms, 500ms, 2s, and 8s) selectable by software
•
Non-maskable interrupt by the first overflow
•
Reset generated by the second overflow
12.1.2 Configuration
Figure 12-1 shows the configuration of the watchdog timer.
WDTCON : Watchdog timer control register
WDTMOD : Watchdog timer mode register
Figure 12-1 Configuration of Watchdog Timer
WDTCON
Data bus
WDP
D Q
R
QN
“5AH”
detection
“0A5H”
detection
WDT counter
R
Reset interrupt
control
WDT reset
WDTINT
Non-maskable interrupt
RESET_S
System reset
T256HZ
WDTCON Write
WDT overflow
WDTMOD