LAPIS Semiconductor ML610421, Руководство пользователя, Страница: 333 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 25 Successive Approximation Type A/D Converter
25 – 6
25.2.6 SA-ADC Control Register 0 (SADCON0)
Address: 0F2F0H
Access: R/W
Access size: 8/16 bits
Initial value: 02H
7 6 5 4 3 2 1 0
SADCON0
     
SACK SALP
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
SADCON0 is a special function register (SFR) used to control the operation of the SA-ADC.
[Description of Bits]
•
SALP (bit 0)
SALP Description
0 Single A/D conversion only (Initial value)
1 Consecutive A/D conversion
This bit is used to select whether A/D conversion is performed once only for each channel or consecutively. When this
bit is set to “0”, A/D conversion is performed once only for each channel and when it is set to “1”, A/D conversion is
performed consecutively according to the settings of the SA-ADC mode register (SADMOD0).
•
SACK (bit 1)
SACK Description
0 HSCLK is set to the range of 375kHz to 625kHz.
1 HSCLK is set to the range of 1.5MHz to 4.2MHz (Initial value)
The SACK bit is used to set an A/D conversion time.
As a conversion time is set by counting HSCLK, set this bit to “0” when HSCLK is set in the range of 375kHz to
625kHz and when HSCLK is set in the range of 1.5MHz to 4.2MHz, set this bit to “1”.
Note:
Set the SACK bit when the SARUN bit of the SADCON1 register is “0” (A/D conversion inactive).
SA-ADC is available only when VDD=1.8V to 3.6V and HSCLK is in the ranges of 375KHz to 625kHz and of 1.5MHz
to 4.2MHz.