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ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 25 Successive Approximation Type A/D Converter
25 – 10
25.3.2 Operation of the Successive Approximation A/D Converter
For direct input, operate SA-ADC in the following procedure.
1. Before starting SA-ADC, start oscillation of the high-speed clock (HSCLK) and wait until the oscillator settles.
2. When HSCLK is within the range from 375KHz to 625kHz, set bit 1 (SACK) of the SA-ADC control register
(SADCON0) to “0” and when HSCLK is within the range from 1.5MHz to 4.2MHz, set it to “1”.
3. Set the SA-ADC mode register 0 (SADMOD0).
4. When bit 0 (SARUN) of SA-ADC control register 1 (SADCON1) is set to “1”, the SA-ADC circuit becomes active
and performs A/D conversion from the lower channel number that is selected in the SA-ADC mode register
(SADMOD0).
5. A/D conversion results are stored in the applicable SA-ADC result registers (SADRnL, SADRnH) and when A/D
conversion of the largest channel number that is selected terminates, an SA-ADC conversion termination interrupt
(ADSINT) is generated.
6. Finally, using bit 0 (SALP) of the SADCON0 register, it is possible to select whether A/D conversion is terminated
(SARUN bit is “0”) or A/D conversion is automatically restarted at termination of A/D conversion of the last channel.
Even if a channel is switched during A/D conversion, the channel that is selected at the start of A/D conversion is
maintained until an A/D conversion termination interrupt occurs.
Figure 25-3 shows the SA-ADC operation timing when channel 0 and channel 1 are selected.
Figure 25-3 SA-ADC Operation Timing at Direct Input
Note:
A/D conversion time in 500kHzRC oscillation mode is 46
µ
s.
HSCLK
SARUN
A/D conversion
on channel 0
A/D conversion
on channel 1
SADINT
A/D operation signal
Conversion time
26.86
µ
s@4.096MHz
Conversion time
26.86
µ
s@4.096MHz