LAPIS Semiconductor ML610421, Руководство пользователя, Страница: 223 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 15 I
2
C Bus Interface
15 – 7
15.2.6 I
2
C Bus 0 Mode Register (I2C0MOD)
Address: 0F2A4H
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
I2C0MOD
— — — I20SYN I20DW1 I20DW0 I20MD I20EN
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
I2C0MOD is a special function register (SFR) to set operating mode.
[Description of Bits]
•
I20EN (bit 0)
The I20EN bit is used to enable the operation of the I
2
C bus interface. Only when the I20EN bit is set to “1”, the
I20ST bit can be set and the I20BB flag starts operation. When the I20EN bit is set to “0”, all the SFRs related to the
I
2
C bus 0 are initialized.
I20EN Description
0 Stops I
2
C operation. (Initial value)
1 Enables I
2
C operation.
•
I20MD (bit 1)
The I20MD bit is used to set the communication speed of the I
2
C bus interface. Standard mode or fast mode can be
selected.
I20MD Description
0 Standard mode (initial value)/ 100kbps@4MHz HSCLK
1 Fast mode / Max. 400kbps@4MHz HSCLK
•
I20DW1, I20DW0 (bits 3, 2)
The I20DW1 and I20DW0 bits are used to set the communication speed reduction rate of the I
2
C bus interface. Set
this bit so that the communication speed does not exceed 100kpbs/400kpbs.
I20DW1 I20DW0 Description
0 0 No communication speed reduction (initial value)
0 1 10% communication speed reduction
1 0 20% communication speed reduction
1 1 30% communication speed reduction
•
I20SYN (bit 4)
The I20SYN bit is used to select whether or not to use the clock synchronization function (handshake function).
Note: This LSI does not support the clock synchronization function or multi-master. Please always set the bit to “0”.
I20SYN Description
0 Clock synchronization is not used. (Initial value)
1 Do not use.
Note:
The I
2
C bus is set so that the communication speed may become 100kbps/400kbps when HSCLK is 4 MHz. Therefore,
when using PLL oscillation (approx. 8.192 MHz) for high-speed oscillation, select 1/2HSCLK at selection of the
HSCLK frequency of FCON0 and select 10% communication speed reduction at selection of I2C0MOD
communication speed reduction. When 500 kHz RC oscillation is used, communication in standard mode (50kbps) is
available with the fast mode by setting I20MD bit to “1”.