LAPIS Semiconductor ML610421, Руководство пользователя, Страница: 107 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 6 Clock Generation Circuit
6 – 14
Figure 6-11 Flow of System Clock Switching Processing (LSCLK
→
HSCLK)
Note:
If the system clock is switched from a low-speed clock to a high-speed clock before the high-speed clock (HSCLK)
starts oscillation, the CPU becomes inactive until HSCLK starts clock supply to the peripheral circuits.
Voltage detection by
BLD
Yes
No
Crystal/ceramic oscillation, PLL oscillation, and
external clock input mode cannot be used. Use
500 kHz RC oscillation mode or low-speed clock
(LSCLK). As necessary, check V
DD
1.3V or higher
for using the 500kHz RC oscillation clock.
VDD
≥
1.8V?
T
WAIT
= 500
µ
s @500 kHz RC oscillation mode
T
WAIT
= 20 ms @Crystal/ceramic oscillation mode
T
WAIT
= 10 ms @PLL oscillation mode
T
WAIT
= 1 ms @Internal clock input mode
Set high-speed oscillation mode before switching the system
clock.
Start of high-speed oscillation
System clock switching (Low-speed clock
→
High-speed clock)
Yes
No
500 kHz RC
used?
When using crystal/ceramic oscillation, PLL
oscillation, or an external clock mode, check that
V
DD
is 1.8V or higher by using BLD.
System clock switching
Wait until oscillation
stabilizes (T
WAIT
)
ENOSC
←
”1”
SYSCLK
←
”1”
High-speed operation
mode