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ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 3 Reset Function
3 – 2
3.2 Description of Registers
3.2.1 List of Registers
Address Name Symbol (Byte) Symbol (Word) R/W Size Initial value
0F001H Reset status register RSTAT

R/W 8

3.2.2 Reset Status Register (RSTAT)
Address: 0F001H
Access: R/W
Access size: 8 bits
Initial value: Undefined
7 6 5 4 3 2 1 0
RSTAT
― ― ― ― ―
WDTR XSTR POR
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 x 1
RSTAT is a special function register (SFR) that indicates the causes by which the reset is generated.
At the occurrence of reset, the contents of RSTAT are not initialized, while the bit indicating the cause of the reset is set
to ”1”. When checking the reset cause using this function, perform write operation to RSTAT in advance and initialize
the contents of RSTAT to “00H”.
[Description of Bits]
•
POR (bit 0)
The POR bit is a flag that indicates that the power-on reset is generated. This bit is set to “1” when powered on.
POR Description
0 Power-on reset not generated
1 Power-on reset generated
•
XSTR (bit 1)
The XSTR bit is a flag that indicates the generation of low-speed oscillation stop detect reset. When low-speed
oscillation stops for the period specified by the low-speed oscillation stop detection time (TSTOP) or more, this bit is
set to “1”.
XSTR Description
0 Low-speed oscillation stop detect reset not occurred
1 Low-speed oscillation stop detect reset occurred
•
WDTR (bit 2)
The WSDTR is a flag that indicates that the watchdog timer reset is generated. This bit is set to “1” when the reset by
overflow of the watchdog timer is generated.
WDTR Description
0 Watchdog timer reset not occurred
1
Watchdog timer reset occurred
Note:
No flag is provided that indicates the occurrence of reset by the RESET_N pin.