LAPIS Semiconductor ML610421, Руководство пользователя, Страница: 77 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 5 Interrupts (INTs)
5 – 8
5.2.7 Interrupt Enable Register 6 (IE6)
Address: 0F016H
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
IE6 E32H

E128H ET1K
  
EPW0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
IE6 is a special function register (SFR) to control enable/disable for each interrupt request.
When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE6 is
not reset.
[Description of Bits]
•
EPW0 (bit 0)
EPW0 is the enable flag for the PWM0 interrupt (PW0INT)
EPW0 Description
0 Disabled (initial value)
1 Enabled
•
ET1K (bit 4)
ET1K is the enable flag for the 1 kHz timer interrupt (T1KINT).
ET1K Description
0 Disabled (initial value)
1 Enabled
•
E128H (bit 5)
E128H is the enable flag for the time base counter 128 Hz interrupt (T128HINT).
E128H Description
0 Disabled (initial value)
1 Enabled
•
E32H (bit 7)
E32H is the enable flag for the time base counter 32 Hz interrupt (T32HINT).
E32H Description
0 Disabled (initial value)
1 Enabled