LAPIS Semiconductor ML610421, Руководство пользователя, Страница: 229 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 15 I
2
C Bus Interface
15 – 13
15.3.3 Operation Waveforms
Figure 15-7 shows the operation waveforms of the SDA and SCL signals and the I20BB flag. Table 15-1 shows the
relationship between communication speeds and HSCLK clock counts.
Figure 15-7 Operation Waveforms of SDA and SCL Signals and I20BB Flag
Table 15-1 Relationship between Communication Speeds and HSCLK Clock Counts
Communication speed
(I20SP)
Speed
reduction
(I20DW1, 0)
t
CYC
t
HD:STA
t
LOW
t
HD:DAT
t
HIGH
t
SU:STA
t
SU:DAT
t
SU:STO
t
BUF
Standard mode
100 k
ｂｐｓ
No reduction 40
φ
18
φ
22
φ
4
φ
18
φ
22
φ
18
φ
18
φ
22
φ
10% reduction 44
φ
20
φ
24
φ
4
φ
20
φ
24
φ
20
φ
20
φ
24
φ
20% reduction 48
φ
22
φ
26
φ
4
φ
22
φ
26
φ
22
φ
22
φ
26
φ
30% reduction 52
φ
24
φ
28
φ
4
φ
24
φ
28
φ
24
φ
24
φ
28
φ
Fast mode
400 k
ｂｐｓ
No reduction 10
φ
4
φ
6
φ
2
φ
4
φ
6
φ
4
φ
4
φ
6
φ
10% reduction 11
φ
4
φ
7
φ
2
φ
4
φ
7
φ
5
φ
4
φ
7
φ
20% reduction 12
φ
5
φ
7
φ
2
φ
5
φ
7
φ
5
φ
5
φ
7
φ
30% reduction 13
φ
5
φ
8
φ
2
φ
5
φ
8
φ
6
φ
5
φ
8
φ
φ
: Period of high-speed clock (HSCLK)
Note
The HSCLK clock count is set so that the communication speed may be set to 100kbps/400kbps when HSCLK is 4
MHz. When the high-speed clock frequency is not 4 MHz, select an I2C0MOD communication speed reduction rate
and an FCON0 HSCLK frequency so that the communication speed may not exceed 100kbps/400kbps.
SDA
Start condition
Repeated start condition
Stop condition
SCL
t
HD:STA
t
LOW
t
HIGH tHD:DAT
t
SU:STA
t
SU:STO
t
BUF
t
SU:DAT
I20BB
t
CYC