LAPIS Semiconductor ML610421, Руководство пользователя, Страница: 134 / 437

ML610Q421/ML610Q422/ML610421User’s Manual
Chapter 9 1 kHz Timer (1kHzTM)
9 – 5
9.3 Description of Operation
By setting the T1KRUN bit of the 1kHz timer control register (T1KCON) to “1”, the 1kHz timer starts counting of the
1kHz timer counter registers L or H (T1KCRL, T1KCRH).
By dividing the T2KHz signal frequency (2.048kHz) of the low-speed timer base counter (LTBC) by the binary/ternary
counter, the timer generates a 1kHz signal. Based on the 1kHz signal, a 1kHz timer interrupt request signal (T1KINT) is
generated by the decimal counters of T1KCRL and T1KCRH. The period of the 1kHz timer interrupt can be selected
between the 10Hz interrupt or 1Hz interrupt using the T1KSEL bit of T1KCON.
When write operation is performed for T1KCRL or T1KCRH, the value of the binary/ternary counter and the value of
T1KCRL or T1KCRH is cleared to “0”.
Data can be read from T1KCRL and T1KCRH. When reading data from T1KCRL or T1KCRH in the 1kHz timer
operation start state, read T1KCRL or T1KCRH twice and check that the values match to prevent the reading of
undefined data during counting.
Figure 9-2 shows an example of the program for reading T1KCL and T1LCRH.
LEA offset T1KCRL ; EA
←
T1KCRL address
MARK:
L ER0, [EA] ; First read
L ER2, [EA] ; Second read
;
CMP ER0, ER1 ; Comparison of T1KCRL and T1CKRH
BNE MARK ; To MARK when not matched.
;
:
Figure 9-2 Example of Program for Reading T1KCRL and T1KCRH