Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 25
Section B: PSoC Core
1,DCh IO_CFG1 StrongP Range[1:0]
P1_LOW_
THRS
SPICLK_ON
_P10
REG_EN IOINT RW : 00
INTERNAL MAIN OSCILLATOR (IMO) REGISTER (page 64 )
1,E8h IMO_TR Trim[7:0] W: 00
1,FAh IMO_TR1 Fine Trim[2:0] RW : 00
x,FEh CPU_SCR1 IRESS SLIM[1:O] IRAMDIS # : 00
1,E2h OSC_CR2 CLK48MEN EXTCLKEN IMODIS RW : 00
INTERNAL LOW SPEED OSCILLATOR (ILO) REGISTER (page 68 )
1,E9h ILO_TR PD_MODE ILOFREQ SATBIASB Freq Trim[3:0] RW : 18
EXTERNAL CRYSTAL OSCILLATOR (ECO) REGISTERS (page 69 )
1,D2h ECO_ENBUS ECO_ENBUS[2:0] RW : 07
1,D3h ECO_TRIM ECO_XGM[2:0] ECO_PL[1:0] RW : 00
1,E1h ECO_CFG ECO_LPM ECO_EXW ECO_EX RW : 00
SLEEP AND WATCHDOG REGISTERS (page 77 )
0,E3h RES_WDT WDSL_Clear[7:0] W : 00
1,EBh SLP_CFG PSSDC[1:0] RW : 0
1,ECh SLP_CFG2 ALT_Buzz [1:0] I2C_ON LSO_OFF RW : 00
1,EDh SLP_CFG3 DBL_TAPS T2TAP [1:0] T1TAP [1:0] T0TAP [1:0] RW : 0x7F
LEGEND
L The and f, expr; or f, expr; and xor f, expr instructions can be used to modify this register.
x An “x” before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used.
C Clearable register or bit(s).
R Read register or bit(s).
W Write register or bit(s).
Summary Table of the Core Registers (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
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