Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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68 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Internal Low Speed Oscillator (ILO)
8.2 Register Definitions
The following register is associated with the Internal Low Speed Oscillator (ILO). The register description has an associated
register table showing the bit structure. The bits in the table that are grayed out are reserved bits and are not detailed in the
register description that follows. Always write reserved bits with a value of ‘0’.
8.2.1 ILO_TR Register
The Internal Low Speed Oscillator Trim Register (ILO_TR)
sets the adjustment for the internal low speed oscillator.
Bit 6: PD_MODE. This bit selects power down mode. Set-
ting this bit high disables the oscillator and current bias
when the ILO is powered down, which results in slower star-
tup time. Setting this bit low keeps the small current bias
running when the ILO is powered down, which results in
faster startup time.
Bit 5: ILOFREQ. When this bit is set, the oscillator operates
at a nominal frequency of 1 kHz, otherwise, it runs at the
default 32 kHz.
Bits 3 to 0: FREQ_TRIM[3:0]. These bits trim the oscillator
frequency. The device-specific value, placed in the trim bits
of this register at boot time, is based on factory testing.
Do
not alter the values in the register .
For additional information, refer to the ILO_TR register on
page 282 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,E9h ILO_TR PD_MODE ILOFREQ Freq Trim[3:0] RW : 18
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