Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 235
STK_PP
0,D1h
21.3.47 STK_PP
Stack Page Pointer Register
This register is used to set the effective SRAM page for stack memory accesses in a multi-SRAM page PSoC device. It is only
used when a device has more than one SRAM page.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on
page 42 in the RAM Paging chapter
.
2:0 Page Bits[2:0] Bits determine which SRAM page is used to hold the stack. See the RAM Paging chapter on page 39
for more information.
000b
SRAM Page 0
001b SRAM Page 1
010b SRAM Page 2
011b SRAM Page 3
100b SRAM Page 4
101b SRAM Page 5
110b SRAM Page 6
111b SRAM Page 7
Individual Register Names and Addresses:
0,D1h
STK_PP : 0,D1h
7 6 5 4 3 2 1 0
Access : POR RW : 0
Bit Name Page Bits[2:0]
Bit Name Description
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