Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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102 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Comparators
The comparator digital interface performs logic process-
ing on one or more comparator signals, provides a latch-
ing capability, and routes the result to other chip
subsystems. The comparator signal is routed through a
lookup table (LUT) function. The other input to the LUT is
the neighboring comparator output. The LUT implements
1 of 16 functions on the two inputs, as selected by the
CMP_LUT register. The LUT output also feeds the set
input upon a reset/set (RS) latch. The latch is cleared by
writing a ‘0’ to the appropriate bit in the CMP_RDC regis-
ter or by a rising edge from the other comparator LUT. The primary output for each comparator is the LUT output or
its latched version. These are routed to the TrueTouch logic
and to the interrupt controller. The comparator LUT output
state and latched state are directly read by the CPU through
the CMP_RDC register. A selection of comparator state may
also be driven to an output pin.
When disabled, the comparators consume no power. Two
active modes provide a full rail-to-rail input range or a
somewhat lower power option with limited input range.
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