PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
179
Full-Speed USB
20.3.12 PMAx_DR Register
The PSoC Memory Arbiter Data Register (PMAx_DR) is
used to read and write to a particular PMA channel by either
the USB SIE or the M8C. Note that a PMA channel may not
be used simultaneously by both the USB SIE and the M8C.
Bits 7 to 0: Data Byte[7:0].
When the M8C writes to this
register, the PMA registers the byte and then stores the
value at the address in SRAM indicated by the PMAx_WA
register.
After the value has been written to SRAM, the PMAx_WA
register is automatically incremented. When the USB SIE
writes to this register, the PMA registers the byte and then
stores the value in SRAM using the sum of the value of the
PMAx_WA register and the USB SIEs received byte count.
When the M8C reads this register, a pre-loaded value is
returned and the PMAx_RA value is automatically incre-
mented.
The new PMAx_RA value is used to fetch the next value
from the SRAM, to be ready for the next read from the chan-
nel's PMAx_DR register. When the USB SIE reads the
PMAx_DR register, it also receives a pre-loaded value,
which triggers the PMA logic to fetch the next value in
SRAM to be ready for the USB SIEs next read request. In all
read cases, the initial pre-load of the first address of the
channel is triggered by writing the first address of the chan-
nel to the channel's PMAx_RA register. Therefore, the
PMAx_RA register must be written after data has been
stored for the channel.
For additional information, refer to the
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,58h
PMA0_DR
Data Byte[7:0]
RW : 00
0,59h
PMA1_DR
Data Byte[7:0]
RW : 00
0,5Ah
PMA2_DR
Data Byte[7:0]
RW : 00
0,5Bh
PMA3_DR
Data Byte[7:0]
RW : 00
0,5Ch
PMA4_DR
Data Byte[7:0]
RW : 00
0,5Dh
PMA5_DR
Data Byte[7:0]
RW : 00
0,5Eh
PMA6_DR
Data Byte[7:0]
RW : 00
0,5Fh
PMA7_DR
Data Byte[7:0]
RW : 00
0,64h
PMA8_DR
Data Byte[7:0]
RW : 00
0,65h
PMA9_DR
Data Byte[7:0]
RW : 00
0,66h
PMA10_DR
Data Byte[7:0]
RW : 00
0,67h
PMA11_DR
Data Byte[7:0]
RW : 00
0,68h
PMA12_DR
Data Byte[7:0]
RW : 00
0,69h
PMA13_DR
Data Byte[7:0]
RW : 00
0,6Ah
PMA14_DR
Data Byte[7:0]
RW : 00
0,6Bh
PMA15_DR
Data Byte[7:0]
RW : 00
Содержание PSoC CY8CTMG20 Series
Страница 4: ...4 Contents Overview Feedback...
Страница 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Страница 54: ...54 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Interrupt Controller Feedback...
Страница 62: ...62 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C General Purpose I O GPIO Feedback...
Страница 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Страница 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Страница 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Страница 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Страница 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Страница 186: ...186 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section E Registers Feedback...
Страница 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...