Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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100 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
I/O Analog Multiplexer
12.2 Register Definitions
The following registers are only associated with the Analog Bus Mux in the CY8CTMG20x and CY8CTST200 PSoC devices
and are listed in address order. Each register description has an associated register table showing the bit structure for that
register. Register bits that are grayed out throughout this document are reserved bits and are not detailed in the register
descriptions that follow. Always write reserved bits with a value of ‘0’.
12.2.1 MUX_CRx Registers
The Analog Mux Port Bit Enable Registers (MUX_CR0,
MUX_CR1, MUX_CR2, MUX_CR3, and MUX_CR4) control
the connection between the analog mux bus and the corre-
sponding pin.
Bits 7 to 0: ENABLE[7:0]. The bits in these registers
enable connection of individual pins to the analog mux bus.
Each I/O port has a corresponding MUX_CRx register.
Setting a bit high connects the corresponding pin to the
analog bus.
For additional information, refer to the MUX_CRx register on
page 271 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,D8h MUX_CR0 ENABLE[7:0] RW : 00
1,D9h MUX_CR1 ENABLE[7:0] RW : 00
1,DAh MUX_CR2 ENABLE[7:0] RW : 00
1,DBh MUX_CR3 ENABLE[7:0] RW : 00
1,DFh MUX_CR4 ENABLE[3:0] RW : 0
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