Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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150 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
SPI
Configuration Register
The configuration block contains 1 register. This register must not be changed while the block is enabled. Note that the SPI
Configuration register is located in bank 1 of the PSoC device’s memory map.
18.2.4 SPI_CFG Register
The SPI Configuration Register (SPI_CFG) is used to con-
figure the SPI.
Bits 7 to 5: Clock Sel [2:0]. Clock Selection. These bits
determine the operating frequency of the SPI Master.
Bit 4: Bypass. This bit determines whether or not the
inputs are synchronized to SYSCLK.
Bit 3: SS_. Slave Select. This bit determines the logic value
of the SS_ signal when the SS_EN_ signal is asserted
(SS_EN_ = 0).
Bit 2: SS_EN_. Slave Select Enable. This active low bit
determines if the slave select (SS_) signal is driven inter-
nally. If it is driven internally, its logic level is determined by
the SS_ bit. If it is driven externally, its logic level is deter-
mined by the external pin.
Bit 1: Int Sel. Interrupt Select. This bit selects which condi-
tion produces an interrupt.
Bit 0: Slave. This bit determines whether the block func-
tions as a master or slave.
For additional information, refer to the SPI_CFG register on
page 261 .
18.2.4.1 SPI Configuration Register Definitions
18.2.5 Related Registers
■
IO_CFG1 Register on page 272.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,29h SPI_CFG Clock Sel[2:0] Bypass SS_ SS_EN_ Int Sel Slave RW : 00
Table 18-5. SPI Configuration Register Descriptions
Bit # Name Access Mode Description
7:5 Clock Sel Read/Write Master
SYSCLK
000b / 2
001b / 4
010b / 8
011b
/ 16
100b / 32
101b / 64
110b
/ 128
111b / 256
4 Bypass Read/Write Master/Slave
0 = All pin inputs are doubled, synchronized.
1 = Input synchronization is bypassed.
3 SS_ Read/Write Slave
0 = Slave selected.
1 = Slave selection is determined from external SS_ pin.
2 SS_EN_ Read/Write Slave
0 = Slave selection determined from SS_ bit.
1 = Slave selection determined from external SS_ pin.
1 Int Sel Read/Write Master/Slave
0 = Interrupt on TX Reg Empty.
1 = Interrupt on SPI Complete.
0 Slave Read/Write Master/Slave
0 = Operates as a master.
1 = Operates as a slave.
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