Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 131
I2C Slave
15.4.3 Status Timing
Figure 15-8 illustrates the interrupt timing for byte complete,
which occurs on the positive edge of the ninth clock (byte +
ACK/NACK) in transmit mode and on the positive edge of
the eighth clock in receive mode. There is a maximum of
three cycles of latency due to the input synchronizer/filter
circuit. As shown, the interrupt occurs on the clock following
a valid SCL positive edge input transition (after the synchro-
nizers). The Address bit is set with the same timing but only
after a slave address has been received. The LRB (Last
Received Bit) status is also set with the same timing but only
on the ninth bit after a transmitted byte.
Figure 15-8. Byte Complete, Address, LRB Timing
Figure 15-9 shows the timing for Stop status. This bit is set
(and the interrupt occurs) two clocks after the synchronized
and filtered SDA line transitions to a ‘1’, when the SCL line is
high.
Figure 15-9. Stop Status and Interrupt Timing
Figure 15-10 illustrates the timing for bus error interrupts.
Bus Error status (and interrupt) occurs one cycle after the
internal Start or Stop detect (two cycles after the filtered and
synchronized SDA input transition).
Figure 15-10. Bus Error Interrupt Timing
3 Cycles
Latency
CLOCK
Transmit: Ninth positive edge SCL
Receive: Eighth positive edge SCL
SCL
SCL_IN
Synchronized)
IRQ
Max
CLOCK
SCL
SDA_IN
Synchronized)
STOP IRQ
and STATUS
SDA
TOP DETECT
CLOCK
SCL
SDA_IN
(Synchronized)
BUS ERROR
and INTERRUPT
SDA
START DETECT
Misplaced Start
Misplaced Stop
CLOCK
SCL
SDA_IN
(Synchronized)
BUS ERROR
and INTERRUPT
SDA
STOP DETECT
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