PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
279
VLT_CR
1,E3h
21.4.20 VLT_CR
Voltage Monitor Control Register
This register is used to set the trip points for POR and LVD.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
in the POR chapter.
5:4
PORLEV[1:0]
Sets the POR level according to the DC Electrical Specifications in the PSoC device data sheet.
3
LVDTBEN
Enables reset of the CPU speed register by LVD comparator output.
2:0
VM[2:0]
Sets the LVD levels per the DC Electrical Specifications in the PSoCdevice data sheet, for those
devices with this feature.
000b
Lowest voltage setting.
001b
010b
011b
100b
101b
110b
111b
Highest voltage setting.
Individual Register Names and Addresses:
1,E3h
VLT_CR: 1,E3h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
Bit Name
PORLEV[1:0]
LVDTBEN
VM[2:0]
Bit
Name
Description
Содержание PSoC CY8CTMG20 Series
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Страница 62: ...62 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C General Purpose I O GPIO Feedback...
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Страница 186: ...186 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section E Registers Feedback...
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