PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
61
General Purpose I/O (GPIO)
6.2.4
IO_CFG1 Register
The Input/Output Configuration Register 1 (IO_CFG1) con-
figures the Port 1 output regulator and set the Interrupt
mode for all GPIO.
Bit 7: StrongP.
Setting this bit increases the drive strength
and edge ratio for high outputs.
Bit 5 and 4: Range[1:0].
These bits select the regulator
output level for Port 1. Available levels are 3.0V, 1.8V, and
2.5V.
Selects the high output level for Port 1 outputs.
Bit 3 P1_LOW_THRS.
This bit reduces the threshold volt-
age of the P1 port input buffers so that there are no compat-
ibility issues when Port 1 is communicating at regulated
voltage levels.
‘0’ is standard threshold of VIH, VIL. ‘1’ is reduce threshold
of VIH, VIL.
Bit 2: SPICLK_ON_P10.
When this bit is set to ‘1’, the SPI
clock is mapped to Port 1 pin 0. Otherwise, it is mapped to
Port 1 pin 3.
Bit 1: REG_EN.
The Register Enable bit (REG_EN) con-
trols the regulator on Port 1 outputs.
Bit 0: IO INT.
This bit sets the GPIO Interrupt mode for all
pins in the CY8CTMG20x, CY8CTST200 PSoC devices.
GPIO interrupts are controlled at each pin by the PRTxIE
registers, and also by the global GPIO bit in the INT_MSK0
register.
For additional information, refer to the
6.2.5
IO_CFG2 Register
The Input/Output Configuration Register 2 (IO_CFG2)
selects output regulated supply and clock rates.
Bits 5 to 3: REG_LEVEL[2:0].
These bits select output
regulated supply.
Bits 1 to 0: REG_CLOCK[1:0].
The Regulated I/O charge
pump can operate with a maximum clock speed of 12 MHZ.
The REG_CLOCK[1:0] bits select clocking options for the
regulator. Setting REG_CLOCK[1:0] to ‘10’ should be used
with 24 MHz SYSCLK and ‘01’ should be used with 6/12
MHz SYSCLK.
For additional information, refer to the
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
1,DCh
StrongP
Range[1:0]
P1_LOW_
THRS
SPICLK_
ON_P10
REG_EN
IOINT
RW : 00
Range[1:0]
Output Level
00
3.0 volts
01
3.0 volts
10
1.8 volts
11
2.5 volts
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
1,DEh
REG_LEVEL[2:0]
REG_CLOCK[1:0]
RW : 00
REG_LEVEL[2:0]
Approx. Regulated Supply (V)
000
3
2.5
1.8
001
3.1
2.6
1.9
010
3.2
2.7
2.0
011
3.3
2.8
2.1
100
3.4
2.9
2.2
101
3.5
3.0
2.3
110
3.6
3.1
2.4
111
3.7
3.2
2.5
REG_CLOCK[1:0]
SYSCLK Clock Rate
10
24 MHz
01
6/12 MHz
Содержание PSoC CY8CTMG20 Series
Страница 4: ...4 Contents Overview Feedback...
Страница 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Страница 54: ...54 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Interrupt Controller Feedback...
Страница 62: ...62 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C General Purpose I O GPIO Feedback...
Страница 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Страница 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Страница 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Страница 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Страница 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Страница 186: ...186 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section E Registers Feedback...
Страница 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
