PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
55
6. General Purpose I/O (GPIO)
This chapter discusses the General Purpose I/O (GPIO) and its associated registers, which is the circuit responsible for inter-
facing to the I/O pins of a PSoC device. The GPIO blocks provide the interface between the M8C core and the outside world.
They offer a large number of configurations to support several types of input/output (IO) operations for both digital and analog
systems. For a complete table of the GPIO registers, refer to the
. For a quick reference of all PSoC
registers in address order, refer to the
Register Reference chapter on page 187
6.1
Architectural Description
The GPIO in the CY8CTMG20x, CY8CTST200 devices are all uniform, except that Port 0 and Port 1 GPIO have stronger
high drive. In addition to higher drive strength, Port 1 GPIO have an option for regulated output level. These distinctions are
discussed in more detail in the section
Port 1 Distinctions on page 56
and
Port 0 Distinctions on page 57
Figure 6-1. GPIO Block Diagram
Drive
Logic
DM1
DM0
Alt. Select
Write PRTxDR
Alt. Data
2:1
Vdd
Note
Alt. Select/
Data is not available
on all pins.
Vdd
5.6k
LDO
REG_EN
Port 1
Only
Vdd
Pin
Drive Modes
DM1
Drive Mode
DM0
Diagram
Number
Data = 0
Data = 1
Alt. Input
(e.g., I2C)
Data
Bus
Read PRTxDR
DM(1:0) = 10b
INBUF
(to GPIO
interrupt logic)
Note
No diode to
Vdd for Port 1
0
0
1
1
0
1
0
1
Resistive Pull Up
Strong Drive
High Impedance
Open Drain
0
1
2
3
Strong
Strong
An. High Z
Strong
Resistive
Strong
High Z
High Z
0.
1.
2.
3.
Содержание PSoC CY8CTMG20 Series
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