Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

Страница: 56 / 308

56 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
General Purpose I/O (GPIO)
6.1.1 General Description
The GPIO contains input buffers, output drivers, and config-
uration logic for connecting the PSoC device to the outside
world.
IO Ports are arranged with (up to) 8 bits per port. Each full
port contains eight identical GPIO blocks. Each GPIO block
is used for the following types of I/O:
■
Digital I/O (digital input and output controlled by soft-
ware)
■
Analog I/O
Each I/O pin also has several drive modes, and interrupt
capabilities. All GPIO pins provide both digital I/O and ana-
log input capability.
All I/O contain the capability to connect to an internal analog
bus. This is described in detail in the
I/O Analog
Multiplexer chapter on page 99 .
Certain pins contain an option to bypass the normal data
path and output from an internal source. An example is I2C
outputs. These are described in
Data Bypass on page 58 .
6.1.2 Digital I/O
One of the basic operations of the GPIO ports is to allow the
M8C to send information out of the PSoC device and get
information into the M8C from outside the device. This is
accomplished by way of the port data register (PRTxDR).
Writes from the M8C to the PRTxDR register store the data
state, one bit per GPIO. In the standard non-bypass mode,
the pin drivers drive the pin in response to this data bit, with
a drive strength determined by the Drive mode setting (see
Figure 6-1 ). The actual voltage on the pin depends upon the
Drive mode and the external load.
The M8C reads the value of a port by reading the PRTxDR
register address. When the M8C reads the PRTxDR register
address, the current value of the pin voltage is translated
into a logic value and returned to the M8C. Note that the pin
voltage can represent a different logic value than the last
value written to the PRTxDR register. This is an important
distinction to remember in situations such as the use of a
read modify write to a PRTxDR register. Examples of read
modify write instructions include AND, OR, and XOR.
The following is an example of how a read modify write, to a
PRTxDR register, could have an unexpected and even inde-
terminate result in certain systems. Consider a scenario
where all bits of Port 1 on the PSoC device are in the strong
0 resistive 1 Drive mode; so that in some cases, the system
the PSoC is in may pull down one of the bits by an external
driver.
mov reg[PRT1DR], 0xFF
and reg[PRT1DR], 0x7F
In the first line of this code, writing a 0xFF to the port causes
the PSoC to drive all pins high through a resistor. This does
not affect any bits that are strongly driven low by the system
the PSoC is in. However, in the second line of code, it can-
not guarantee that only bit 7 is the one set to a strong 0
(zero). Because the AND instruction first reads the port, any
bits that are currently driven low externally are read as a 0.
These zeros are then written back to the port. When this
happens, the pin goes into a strong 0 state; therefore, if the
external low drive condition ends in the system, the PSoC
keeps the pin value at a logic 0.
6.1.3 Analog and Digital Inputs
Analog signals pass into the PSoC device core from device
pins through a resistive path. For analog signals, the GPIO
block is typically configured into a High Impedance Analog
Drive mode (High Z). The mode turns off the Schmitt trigger
on the input path, which may reduce power consumption
and decrease internal switching noise when using a particu-
lar I/O as an analog input.
All modes, except High Impedance Analog, allow digital
inputs. The most useful digital input modes are Resistive
Pull Up (DM1, DM0 = 00b with Data = 1) or a fully high
impedance input using open drain (DM1, DM0 = 11b with
Data = 1).
6.1.4 Port 1 Distinctions
Port 1 has two differences from the other GPIO ports. It has
stronger high drive (as does Port 0) and it has an option for
regulating all outputs to a 3V/2.5V/1.8V level when in strong
drive mode. Refer to the device data sheet for the different
current sourcing specifications of Port 1.
By setting the REG_EN bit in the IO_CFG1 register, Port 1
can be configured to drive strong high to a regulated 3V/
2.5V/1.8V level. If REG_EN is set low, Port 1 pins drive to
Vdd in strong drive mode.
In Resistive High Drive mode ([DM1, DM0] = 00), the pins
pull up to the
chip Vdd level regardless of the regulator set-
ting for this port. Only Strong Drive mode allows for the out-
puts to be driven to the regulated level. When the REG_EN
bit is set high, pins configured for strong drive to regulated
level, while those in resistive pull up mode drive to Vdd.
In their default state, all Port 1 I/O prevent DC current from
flowing into the pin when the pin voltage is above the chip
Vdd. This feature resolves the problem where the PSoC
holds down the system I2C bus or provides a current leak-
age path from a powered peripheral during PSoC power
down or reset.
The open drain driver is capable of sinking 24 mA current
(required for sinking LEDs used for backlighting) and main-
taining a logic low state.
Regulated output level can be selected by bits 4 and 5 in the
IO_CFG1 register. For 3V output level, the chip Vdd should
be greater than 3.1V. For 2.5V output, the chip Vdd should
[+] Feedback