Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 99
12. I/O Analog Multiplexer
This chapter explains the device-wide I/O Analog Multiplexer for the CY8CTMG20x and CY8CTST200 PSoC devices and
their associated registers. For a quick reference of all registers in address order, refer to the
Register Reference chapter on
page 187 .
12.1 Architectural Description
The CY8CTMG20x and CY8CTST200 PSoC devices con-
tain an enhanced analog multiplexer (mux) capability. This
function allows many I/O pins to connect to a common inter-
nal analog global bus.
You are able to connect any number of pins simultaneously,
and dedicated support circuitry allows selected pins to be
alternately charged high or connected to the bus. The ana-
log global bus can be connected as a comparator input.
Figure 12-1 shows a block diagram of the I/O analog mux
system.
Figure 12-1. I/O Analog Mux System
For each pin, the mux capability exists in parallel with the
normal GPIO cell, shown in
Figure 12-2 . Normally, the asso-
ciated GPIO pin is put into a high impedance state for these
applications, although there are cases where the GPIO cell
is configured by the user to briefly drive pin initialization
states as described ahead.
Pins are individually connected to the internal bus by setting
the corresponding bits in the MUX_CRx registers. Any num-
ber of pins can be enabled at the same time. At reset, all of
these mux connections are open (disconnected).
Figure 12-2. I/O Pin Configuration
Analog
Mux
IO Pin
Device
IO Pin
Analog Mux Bus
IO
Pin
IO Pin
GPIO
Pin
Switch Enable
(MUX_CRx.n)
Analog Mux Bus
Discharge
Clock
Break-
Before-Make
Circuitry
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