Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 77
Sleep and Watchdog
10.3 Register Definitions
The following registers are associated with Sleep and Watchdog operations and are listed in address order. Each register
description has an associated register table showing the bit structure for that register. The bits that are grayed out in the
tables below are reserved bits and are not detailed in the register descriptions. Always write reserved bits with a value of ‘0’.
For a complete table of the Sleep and Watchdog registers, refer to the
Summary Table of the Core Registers on page 24 .
10.3.1 RES_WDT Register
The Reset Watchdog Timer Register (RES_WDT) clears the
watchdog timer (a write of any value) and clears both the
watchdog timer and the sleep timer (a write of 38h).
Bits 7 to 0: WDSL_Clear[7:0]. The Watchdog Timer
(WDT) write-only register is designed to timeout at three
sleep timer rollover events. If only the WDT is cleared, the
next Watchdog Reset (WDR) occurs anywhere from two to
three times the current sleep interval setting. If the sleep
timer is near the beginning of its count, the watchdog time-
out is closer to three times.
However, if the sleep timer is very close to its terminal
count , the watchdog timeout is closer to two times. To
ensure a full three times timeout, clear both the WDT and
the sleep timer. In applications that need a realtime clock
and cannot reset the sleep timer when clearing the WDT, the
duty cycle at which the WDT must be cleared is no greater
than two times the sleep interval.
For additional information, refer to the RES_WDT register
on page 253 .
10.3.2 SLP_CFG Register
The Sleep Configuration Register (SLP_CFG) sets the sleep
duty cycle.
The value placed in this register is based upon factory test-
ing.
Bits 7 and 6: PSSDC[1:0]. The Power System Sleep Duty
Cycle bits set the sleep duty cycle.
For additional information, refer to the SLP_CFG register on
page 283 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,E3h RES_WDT WDSL_Clear[7:0] W : 00
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,EBh SLP_CFG PSSDC[1:0] RW : 0
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