Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 145
18. SPI
This chapter presents the Serial Peripheral Interconnect (SPI) and its associated registers. For a complete table of the SPI
registers, refer to the
Summary Table of the System Resource Registers on page 106 . For a quick reference of all PSoC reg-
isters in address order, refer to the Register Reference chapter on page 187 .
18.1 Architectural Description
The Serial Peripheral Interconnect (SPI) block is a dedi-
cated master or slave SPI. The SPI slave function requires
three inputs: Clock, Data, and SS_ (unless the SS_ is forced
active with the SS_bit in the configuration register).
Figure 18-1. SPI Block Diagram
18.1.1 SPI Protocol Function
The SPI is a Motorola™ specification for implementing full-
duplex synchronous serial communication between devices.
The 3-wire protocol uses both edges of the clock to enable
synchronous communication without the need for stringent
setup and hold requirements.
Figure 18-2 shows the basic
signals in a simple connection.
Figure 18-2. Basic SPI Configuration
A device can be a master or slave. A master outputs clock
and data to the
slave device and inputs slave data. A slave
device inputs clock and data from the master device and
outputs data for input to the master. Together, the master
and slave are essentially a circular Shift register, where the
master generates the clocking and initiates data transfers.
A basic data transfer occurs when the master sends eight
bits of data, along with eight clocks. In any transfer, both
master and slave transmit and receive simultaneously. If the
master only sends data, the received data from the slave is
ignored. If the master wishes to receive data from the slave,
the master must send dummy bytes to generate the clocking
for the slave to send data back.
SPI Block
Registers
SYSCLK
DATA_OUT DATA_IN
CLK_IN CLK_OUT
INT
SS_
SCLK
MOSI,
MISO
SCLK
MOSI,
MISO
CONFIGURATION[7:0] CONTROL[7:0]
TRANSMIT[7:0] RECEIVE[7:0]
SPI Master SPI Slave
MOSI
SCLK
SS_ MISO
MOSI
MISO
SCLK
Data is output by
both the Master
and Slave on
one edge of the
clock.
Data is registered at the
input of both devices on the
opposite edge of the clock.
MOSI
SCLK
SS_
MISO
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