Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 81
Sleep and Watchdog
10.4.4 Watchdog Timer
On device boot up, the Watchdog Timer (WDT) is initially
disabled. The PORS bit in the System Control register con-
trols the enabling of the WDT. Upon boot, the PORS bit is
initially set to '1', indicating that either a POR or XRES event
occurred. The WDT is enabled by clearing the PORS bit.
After this bit is cleared and the WDT enabled, it cannot be
disabled. (The PORS bit cannot be set to '1' in firmware;
only cleared.)
The only way to disable the watchdog function after it is
enabled is through a subsequent POR or XRES. Even
though the WDT is disabled during the first time through ini-
tialization code after a POR or XRES, write all code as if it is
enabled (that is, periodically review the WDT). This is
because in the initialization code after a WDR event, the
watchdog timer is enabled so all code must be aware of this.
The watchdog timer is three counts of the sleep timer inter-
rupt output. The watchdog interval is three times the
selected sleep timer interval. The available selections for the
watchdog interval are shown in
Table 10-1 . When the sleep
timer interrupt is asserted, the watchdog timer increments.
When the counter reaches three, a terminal count is
asserted. This terminal count is registered by the 32 kHz
clock. Therefore, the WDR (Watchdog Reset) signal goes
high after the falling edge of the 32 kHz clock and held
asserted for one cycle (30
μ
s nominal). The flip-flop that
registers the WDT terminal count is not reset by the WDR
signal when it is asserted, but is reset by all other resets.
This timing is shown in
Figure 10-5 .
Figure 10-5. Watchdog Reset
After enabled, periodically clear the WDT in firmware. Do
this with a write to the RES_WDT register. This write is data
independent, so any write clears the watchdog timer. (Note
that a write of 38h also clears the sleep timer.) If for any rea-
son the firmware fails to clear the WDT within the selected
interval, the circuit asserts WDR to the device. WDR is
equivalent in effect to any other reset. All internal registers
are set to their reset state. (See the table titled
Reset Func-
tionality on page 141 .) An important aspect to remember
about WDT resets is that RAM initialization can be disabled
(IRAMDIS is in the CPU_SCR1 register). In this case, the
SRAM contents are unaffected; so that when a WDR
occurs, program variables are persistent through this reset.
In practical application, it is important to know that the
watchdog timer interval can be anywhere between two and
three times the sleep timer interval. The only way to guaran-
tee that the WDT interval is a full three times that of the
sleep interval is to clear the sleep timer (write 38h) when
clearing the WDT register. However, this is not possible in
applications that use the sleep timer as a realtime clock. In
the case where firmware clears the WDT register without
clearing the sleep timer, this occurs at any point in a given
sleep timer interval. If it occurs just before the terminal count
of a sleep timer interval, the resulting WDT interval is just
over two times that of the sleep timer interval.
SLEEP INT
WD RESET
(WDR)
CLK32K
2 WD COUNT 3 0
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