Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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278 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
OSC_CR2
1,E2h
21.4.19 OSC_CR2
Oscillator Control Register 2
This register is used to configure various features of internal clock sources and clock nets.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on
page 112 in the Digital Clocks chapter.
4 CLK48MEN This is the 48 MHz clock enable bit.
0
Disables the 48 MHz clock.
1 Enables the 48 MHz clock.
2 EXTCLKEN External Clock Mode Enable.
0
Disabled. Operate from internal main oscillator.
1 Enabled. Operate from the clock supplied at P1[4] or P1[1] based upon the TSYNC bit in
CPU_SCR1.
1 IMODIS Internal Oscillator Disable. This bit can be set to save power when using an external clock on P1[4].
0
Enabled. Internal oscillator enabled.
1 Disabled.
Note This bit must not be set high in the same instruction that sets EXTCLKEN high, but it can be set
in the next instruction. Also, this bit must not be set high if the external clock frequency is less than 6
MHz.
When switching from external clock to internal clock, the IMO must be enabled for at least 10
μ
s
before the transition to internal clock. Refer to Switch Operation on page 110 .
Individual Register Names and Addresses:
1,E2h
OSC_CR2 : 1,E2h
7 6 5 4 3 2 1 0
Access : POR RW : 0 RW : 0 RW : 0
Bit Name CLK48MEN EXTCLKEN IMODIS
Bit Name Description
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