Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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112 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Digital Clocks
14.2 Register Definitions
The following registers are associated with the Digital Clocks and are listed in address order. Each register description has an
associated register table showing the bit structure for that register. The bits in the tables that are grayed out throughout this
manual are reserved bits and are not detailed in the register descriptions that follow. Always write reserved bits with a value of
‘0’. For a complete table of digital clock registers, refer to the
“System Resources Register Summary” on page 106 .
14.2.1 USB_MISC_CR Register
The USB Miscellaneous Control Register controls the clocks
to the USB block, to make the IMO work with better accu-
racy for the USB part and to disable the single ended input
of the USBIO in the case of a non-USB part.
Bit 2: USB_SE_EN. The single ended outputs of USBIO is
enabled or disabled based upon this bit setting. Set this bit
to '1' when using this part as a USB part for USB transac-
tions to occur. Set this bit to '0' to disable single ended out-
puts of USBIO. The DPO, DMO are held at logic high state
and RSE0 is held at a low state.
Note Bit [1:0] of the USBIO_CR1 register is also affected
depending on this register setting. When this bit is '0'
(default), regardless of the DP and DM state, the DPO and
DMO bits of USBIO_CR1 are '11b'.
Bit 1: USB_ON. This bit is used by the IMO DAC block to
either work with better DNL consuming higher power, or with
sacrificed DNL consuming lower power. Set this bit to '1'
when the part is used as a USB part. A '0' runs the IMO with
sacrificed DNL by consuming less power. A '1' runs the IMO
with better DNL by consuming more power.
Bit 0: USB_CLK_ON. This bit either enables or disables
the clocks to the USB block. It is used to save power in
cases when the device need not respond to USB traffic. Set
this bit to '1' when the device is used as a USB part.
When this bit is a ‘0’, all clocks to the USB block are driven.
The device does not respond to USB traffic and none of the
USB registers, except IMO_TR, IMO_TR1 and
USBIO_CR1, listed in the
Register Definitions on page 171
are writable.
When this bit is a ‘1’, clocks are not blocked to the USB
block. The device responds to USB traffic depending on the
other register settings mentioned under
Register Definitions
in the Full-Speed USB chapter on page 165 .
For additional information, refer to the USB_MISC_CR reg-
ister on page 267 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,BDh USB_MISC_CR USB_SE_EN USB_ON USB_CLK_ON RW : 0
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