Kintex UltraScale KCU1500 Acceleration Development Board
48
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 6:
Install, Bring-Up, and Use
More information on
map_connect
can be found in the
SDAccel Environment User Guide
(UG1023)
[Ref 4]
and the
SDAccel Environment Optimization Gui
de (UG1027)
[Ref 5]
.
Clock Frequency
By default, the kernel clock of the platform runs at 300 MHz, and the optional kernel clock
2 runs at 500 MHz. Unless kernel clock 2 is explicitly used by an RTL kernel, all kernel data
path logic is synchronous to kernel clock. See platform clocking for details.
To override the default kernel clock frequency with a different frequency specification, the
XOCC
script would contain the following switch format:
--kernel_frequency <freq_in_mhz>
For example, to specify that the kernel clock frequency should target 200 MHz rather than
the default of 300 MHz:
--kernel_frequency 200
If kernel clock 2 is used by the RTL kernel, then the switch takes a key-value format, where
kernel clock is identified by key
0
and kernel clock 2 is identified by key
1
.
For example, to specify that the kernel clock frequency should target 250 MHz rather than
the default of 300 MHz, and that kernel clock 2 should target 400 MHz rather than the
default of 500 MHz, as follows:
--kernel_frequency 0:250|1:400
To instruct the SDAccel System Compiler to use the optional kernel clock 2, a user's RTL
kernel must implement the following input port naming convention. The user is responsible
for ensuring proper clock domain crossing from the kernel clock to kernel clock 2 in the
ingress direction (slave interface), and from kernel clock 2 to kernel clock in the egress
direction (master interface(s)).
°
ap_clk
, which the SDAccel System Compiler will drive with the kernel clock
°
ap_rst_n
, which the SDAccel System Compiler will drive with the active-low reset
synchronous to kernel clock
°
ap_clk_2
, which the SDAccel System Compiler will drive with the kernel clock 2
°
ap_rst_n_2
, which the SDAccel System Compiler will drive with the active-low
reset synchronous to kernel clock 2
See the
SDAccel Environment User Guide
(UG1023)
[Ref 4]
and the
SDAccel Environment
Optimization Gui
de (UG1027)
[Ref 5]
for kernel frequency specification, RTL kernels, and
related topics.
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