Kintex UltraScale KCU1500 Acceleration Development Board
20
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 3:
Hardware Platform
SDAccel OpenCL Programmable Region IP and the
Programmable Region
Instantiated within the reconfigurable expanded region, the SDAccel OpenCL
Programmable Region IP core instance is used to designate a level of platform hierarchy to
be used with the SDAccel System Compiler and C/C++, OpenCL, and RTL user kernels. While
the IP instance in the IP integrator block diagram of the platform contains only a simple
“add one” placeholder kernel (also known as a
training
kernel, which is necessary to avoid
excessive logic pruning throughout the platform), the IP instance importantly designates a
logical programmable region level of hierarchy in the resulting DSA that the SDAccel
System Compiler later replaces with user-defined kernels and the surrounding AXI
connectivity to the remainder of the platform.
As previously described in
Expanded Partial Reconfiguration in Chapter 2
, recall that
although only the Programmable Region is replaced with user-defined kernel content
during the SDAccel System Compiler flow, the generated partial bitstream corresponds to
the entirety of the expanded region level of hierarchy. Because the expanded region is a
superset of the Programmable Region and other platform logic, each SDAccel System
Compiler runs place and route on the entirety of that expanded region, allowing the user
kernels to be flexibly placed and routed together with the remainder of the expanded
region logic; thereby providing higher fabric capacity to the user kernel content than if only
the Programmable Region were contained in the partial bitstream.
The following figure shows the SDAccel OpenCL Programmable Region IP core instance.
• The
S_AXI
interface is an AXI4-Lite slave interface, allowing host control of user
kernels.
X-Ref Target - Figure 3-8
Figure 3-8:
SDAccel OpenCL Programmable Region IP Core Instance and its Interfaces
Send Feedback
