Kintex UltraScale KCU1500 Acceleration Development Board
39
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 5:
Implementation
2. For more opportunity to interact with Vivado, including the ability to refine the block
diagram before running synthesis, to report timing between stages, and so forth; begin
by invoking
vivado -source create_design.tcl
from the Linux command line.
This creates the new project and produces the validated block diagram. From within the
same Vivado session, proceed with manually invoking
source run_synth.tcl
,
source run_impl.tcl
, and
source write_dsa.tcl
in sequence, after each stage
and any additional desired operations have successfully completed.
Note:
If you do not want to create a DSA for the SDAccel Environment you can simply generate a
bitstream after
run_impl.tcl
completes, following option 2 above but forgoing the use of
write_dsa.tcl
.
The following figure illustrates the invocation of the two flows, their stages, as well as
interim and final outputs. The blue shows the more automated option 1 usage flow
(described above), and the red shows the more manual option 2 usage flow (described
above).
X-Ref Target - Figure 5-1
Figure 5-1:
Platform Reference Design Implementation Script Usage Flow Options
create_design.tcl
run_synth.tcl
run_impl.tcl
write_dsa.tcl
Vivado IP Integrator
block diagram
Synthesized IP cores
and top-level design
Implemented (placed
and routed) design
.dsa file for use with
SDAccel
vivado -source create_design.tcl
vivado -source run.tcl
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