Kintex UltraScale KCU1500 Acceleration Development Board
29
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 3:
Hardware Platform
For example, if user kernel logic operating entirely on the kernel clock domain was
constrained to the default of 300 MHz (3.333ns period) but finished implementation with a
-235ps WNS setup violation on paths limited to the kernel clock domain, then the SDAccel
runtime will adjust the kernel clock MMCM source to produce a 280 MHz (3.568ns) kernel
clock instead. The new operating frequency, if any, is reported as a warning near the end of
the SDAccel System Compiler flow. Timing paths on other clock domains must successfully
close timing in the SDAccel System Compiler flow, however; and for that reason, the
HIGH_PRIORITY
clock property is used as described in
Design Constraints Detail in
Chapter 5
.
Platform Resets
A Processor System Reset IP core instance exists per clock domain, and drives a reset output
to the reset interfaces of the IP core, synchronous to that domain. Generally:
• The
dcm_locked
(clock is stable) input of a reset controller operating synchronously
to a clock produced by a Clocking Wizard IP instance is driven by the
locked
output of
that instance.
• The
dcm_locked
(clock is stable) input of a reset controller operating synchronously
to the XDMA clock is driven by
user_lnk_up
output of the XDMA IP instance.
• The
ext_reset_n
(reset source) input of a reset controller in the reconfigurable
expanded region is driven by the memory-mapped
gate_pr
GPIO IP core instance, as
described in
Partial Reconfiguration Isolation
.
Note:
The DDR4 IP reset controllers do not use this scheme and are reset by the IP instances
themselves.
The platform reset methodology is simple, except for the need to isolate the expanded
region logic during partial reconfiguration, which is described in the following section.
Partial Reconfiguration Isolation
The XDMA IP is contained in the static base region level of hierarchy, and must be isolated
from changes to the reconfigurable expanded region. In this way, the PCIe link is not
disrupted when a new binary is downloaded to the reconfigurable expanded region area of
the accelerator device.
The device driver manages this non-disruptive partial bitstream download process with the
aid of the platform hardware. Contained within the
pr_isolation_expanded
sub-hierarchy of the static base region, a memory-mapped GPIO IP core instance named
gate_pr
is used to hold the reconfigurable expanded region logic, as well as flip-flops at
the boundary of the static base region, in reset.
Send Feedback
