Kintex UltraScale KCU1500 Acceleration Development Board
17
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 3:
Hardware Platform
IMPORTANT:
Derived platforms with user modifications must not use IDs identical to the reference
design platform. See the SDAccel Environment Platform Development Guide (UG1164)
[Ref 2]
for more
information on device drivers for SDx™ accelerator devices.
As shown in the following figure, the XDMA IP is customized to provide the host access to
up to 4MB of memory-mapped platform resources, over its AXI4-Lite control interface.
As shown in the following figure, the XDMA IP is customized to use two DMA read and two
DMA write channels, with 32 read IDs and 16 write IDs, for a balance of performance and
area.
See the IP Customization GUI of the XDMA instance in the provided platform reference
design for all XDMA IP customization settings. See the
DMA Subsystem for PCI Express v3.0
Product Guide
(PG195)
[Ref 3]
for more information on the XDMA IP core, its features, and
customizations options.
X-Ref Target - Figure 3-4
Figure 3-4:
XDMA IP customization - PCIe: BARs Tab
X-Ref Target - Figure 3-5
Figure 3-5:
XDMA IP Customization - PCIe: DMA Tab
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