Kintex UltraScale KCU1500 Acceleration Development Board
11
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 2:
Platform Characteristics
Sparse Memory Connectivity
For maximum bandwidth, the Xilinx Acceleration KCU1500 4DDR Expanded Partial
Reconfiguration platform connects the SDAccel OpenCL Programmable Region IP core (and
therefore the Programmable Region for user kernels) to the four DDR4 memory controllers
using an AXI4 memory-mapped 512-bit data path per instance. It also connects the Xilinx
DMA subsystem for PCI Express to all four DDR4 memory controllers using an AXI4
memory-mapped 256-bit data path per instance. To simplify wiring so that routing and
timing closure are feasible, the platform implements sparse connectivity. Specifically, within
the platform:
• The host has access to the full 16GB of DDR4 SDRAM global memory space.
• Each of the four master interfaces on the SDAccel OpenCL Programmable Region IP
core (and therefore the Programmable Region for user kernels) has access to one
channel of DDR4 SDRAM; that is, 4GB of the 16GB space.
However, users can specify the required connectivity mapping of their kernels to master
interfaces such that any kernel can access the amount of global memory it requires, up to
and including all four channels. The SDAccel System Compiler then implements the
appropriate wiring between kernels and Programmable Region master interfaces. In this
way, while the default connectivity of the system does not impose an undue burden on the
Vivado implementation tools, the user may specify higher connectivity at the expense of
more challenging routing and timing closure. An abstract representation of the kernel to
global memory connectivity is shown in
Figure 2-3
. See
User-Specified Connectivity in
Chapter 6
for more information.
X-Ref Target - Figure 2-3
Figure 2-3:
Sparse Memory Connectivity with User-Defined Kernel to Global Memory
Connectivity
Programmable Region
User
kernel 1
User
kernel
N
...
AXI SmartConnect
AXI SmartConnect
AXI SmartConnect
AXI SmartConnect
User-defined
connectivity
User
kernel 2
DDR4 channel 0
Memory Controller
DDR4 channel 1
Memory Controller
DDR4 channel 2
Memory Controller
DDR4 channel 3
Memory Controller
Xilinx DMA
Subsystem for PCIe
AXI SmartConnect
Host
(via PCIe)
256
512
512
512
512
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