Kintex UltraScale KCU1500 Acceleration Development Board
13
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 2:
Platform Characteristics
°
Input pipeline stages on the master interfaces connected to the host are variously
floorplanned to each SLR, straddling the boundary to facilitate known SLR crossing.
The following figure shows a simplified representation of the IP partitioning described
above (and is not precisely representative of the device floorplan), where:
°
The red horizontal line represents the boundary between the two SLRs.
°
The small white squares represent pipeline stages floorplanned to a given SLR.
°
The small gray squares with dotted outlines represent pipeline stages that connect
to the Programmable Region and which, like the Programmable Region, are not
floorplanned and can be placed on either side of the SLR as determined by the
implementation tools.
Note:
The pipeline stages are actually submodules of SmartConnect IP instances, but for clarity are
shown as separate entities in the simplified picture.
The combination of static base and reconfigurable expanded region partitioning, with the
optimal configuration and careful floorplanning of IP instances, together facilitate the
necessary controlled SLR crossing in the KU115 device to effectively utilize both SLRs.
X-Ref Target - Figure 2-4
Figure 2-4:
Simplified Representation of IP Partitioning for Controlled SLR Crossing
AXI SmartConnect
DDR4 channel 2
Memory Controller
AXI SmartConnect
DDR4 channel 3
Memory Controller
AXI SmartConnect
DDR4 channel 0
Memory Controller
DDR4 channel 1
Memory Controller
AXI SmartConnect
AXI SmartConnect
Xilinx DMA
Subsystem for PCIe
Lower SLR
Upper SLR
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