Kintex UltraScale KCU1500 Acceleration Development Board
16
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 3:
Hardware Platform
Host Connectivity
The platform implements connectivity to the host computer using the Xilinx DMA
subsystem for PCI Express® (PCIe) IP, which contains a scatter-gather DMA and a PCIe 3.x
integrated block.
For best performance on the Kintex® UltraScale™ KCU1500 Acceleration development
board, the PCIe integrated block can negotiate a link up to Gen3 x8 connectivity, or 8.0 GT/s.
The Kintex UltraScale KCU1500 Acceleration development board supplies a 100 MHz
reference clock and uses PCIe block location
X0Y0
. The platform uses an AXI
memory-mapped interface operating at 250 MHz with a 256-bit data width. The basic
customization of the Xilinx DMA subsystem for PCIe IP core (herein referred to as the XDMA
IP core) is shown in the following figure.
For compatibility with the
provided kernel mode and
HAL drivers, the XDMA IP instance is
customized to use Vendor ID
0x10EE
(Xilinx Vendor ID), Device
IDs
0x4B27
and
0x4B28
,
and Subsystem ID
0x4340
.
X-Ref Target - Figure 3-3
Figure 3-3:
XDMA IP customization - Basic Tab
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