Kintex UltraScale KCU1500 Acceleration Development Board
28
UG1234 (v2017.1) June 20, 2017
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Chapter 3:
Hardware Platform
The XDMA, AXI4-Lite control, kernel clock, kernel clock 2, and AXI Performance Monitor
clocks are all derived from the PCIe 100 MHz differential
ref_clk
top-level input from the
Kintex UltraScale KCU1500 Acceleration development board.
The following figure shows the
base_clocking
sub-hierarchy of the static base region.
Contained within that region are the reference clock that drives clock buffer IP instances
buf_refclk_ibuf
and
buf_refclk_bufg
, for serial transceiver and fabric clock access,
respectively. The
buf_refclk_bufg
instance then drives the three Clocking Wizard IP
instances in the system.
Although the AXI4-Lite control and AXI Performance Monitor clocks are both produced
from a single Clocking Wizard IP instance using a PLL, the kernel clock and kernel clock 2
are each generated from a separate, memory-mapped Clocking Wizard IP instance using an
MMCM. This is to support the automatic frequency scaling feature of the SDAccel Software
Platform runtime, which at the time the partial bitstream is loaded, adjusts the operating
frequency of the kernel clock and kernel clock 2 independently in accordance with the
timing results of the implemented design. See
Timing Closure in Chapter 6
for details.
AXI Performance
Monitor
Clocking Wizard IP
instance
clkwiz_sysclks
300 MHz
Exclusive to trace offload
hardware infrastructure
DDR4 memory
controller clock
(one per instance)
DDR4 IP instance
ddrmem_[0|1|2|3]
300 MHz
Within the
ddrmem_[0|1|2|3]
IP instance, and for the AXI
connectivity to the
corresponding SmartConnect IP
instance
X-Ref Target - Figure 3-15
Figure 3-15:
Clocking Resources in Static Base Region base_clocking Sub-Hierarchy
Table 3-1:
Platform Clock Domains
(Cont’d)
Clock Domain
Source
Frequency
Use in Platform
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