Kintex UltraScale KCU1500 Acceleration Development Board
25
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 3:
Hardware Platform
°
The
M00_AXI
interface of each is connected to the corresponding DDR4 IP
instance; therefore, the
aclk
port of each instance is driven by the connected AXI
interface clock DDR4 IP instance. See
Sparse Memory Connectivity in Chapter 2
for
context.
The following figure shows the connectivity from the XDMA IP master, through the
dma_pf_demux
to produce the management and user paths, to the two AXI Interconnect
instances which connect to the relevant peripherals on each path.
• Host access using XDMA IP is the control path master of the platform. The XDMA IP is
configured for two physical functions, which are then split into the two distinct
low-speed, 32-bit AXI-Lite paths using the
dma_pf_demux
instance in the static base
region. A management path corresponds system peripherals, while a user path controls
user kernels and associated peripherals.
• The management path driven by the
dma_pf_demux S_AXI_MGNTPF
interface
provides the XDMA IP master with memory-mapped access to peripherals in both the
static base regions using a 1x13 AXI Interconnect IP and a downstream 1x4 AXI
Interconnect IP in the reconfigurable expanded region. Those two AXI Interconnect
instances are isolated from one another by partial reconfiguration isolation logic (see
Partial Reconfiguration Isolation
for details).
• The user path driven by the
dma_pf_demux S_AXI_USERPF
interface provides the
XDMA IP master with memory-mapped access to peripherals in both the static base
region using a 2x3 AXI Interconnect IP and a downstream 1x3 AXI Interconnect IP in the
reconfigurable expanded region. Those two AXI Interconnect instances are isolated
from one another by partial reconfiguration isolation logic (see
Partial Reconfiguration
Isolation
for details). The second master interface on the static base region 2x3 AXI
Interconnect IP allows the management path to access all peripherals on the user path.
X-Ref Target - Figure 3-13
Figure 3-13:
AXI4-Lite Control Path Connectivity
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