Kintex UltraScale KCU1500 Acceleration Development Board
27
UG1234 (v2017.1) June 20, 2017
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Chapter 3:
Hardware Platform
After tabulation, key profiling data is transformed using an AXI4-Stream Subset Converter
and buffered in an AXI-Stream FIFO for interpretation by the SDx Environments application
profiling feature. AXI Register Slice instances on the control path ease automatic
placement.
Clocking and Reset
The following sections describe clocking and reset on the Kintex UltraScale KCU1500
Acceleration development board:
•
Platform Clocking
•
Platform Resets
•
Partial Reconfiguration Isolation
Platform Clocking
The following table describes the primary clock domains of the platform, their sources,
frequency, and usage in the platform.
Table 3-1:
Platform Clock Domains
Clock Domain
Source
Frequency
Use in Platform
XDMA
XDMA IP core
250 MHz
Within XDMA IP core, and its AXI
master interfaces
AXI4-Lite control
Clocking Wizard IP
instance
clkwiz_sysclks
50 MHz
The majority of AXI4-Lite control
paths throughout the platform
Kernel clock
Clocking Wizard IP
instance
clkwiz_kernel
Default of 300 MHz.
Can be overridden by
the user at compile
time, as well as
automatically scaled at
runtime.
The clock domain for C/C++ and
OpenCL kernels, and the primary
clock domain for RTL kernels.
Also used for the AXI
memory-mapped connections
between the Programmable
Region and AXI SmartConnect IP
instances.
Kernel clock 2
Clocking Wizard IP
instance
clkwiz_kernel2
Default of 500 MHz.
Can be overridden by
the user at compile
time, as well as
automatically scaled at
runtime.
The optional secondary clock
domain for RTL kernels. When
utilized, available internal to
those RTL kernels only.
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